To facilitate circuit correction, while increasing the design freedom of the whole circuit by a method, wherein in a standard mode semiconductor integrated circuit, unwired dummy cells are arranged beforehand on a chip.

In a design of a semiconductor device circuit, first the chip layout on a chip 4 is automatically arranged and wired, using an automatic tool based on the circuit connection data. Next, dummy cells 3, 3A, 3B having no wiring data in high frequency of use having horizontal directional power supply wiring and ground wiring are arranged in the vacant regions between function cells causing the floating of ground wiring. In such a constitution, since the dummy cells 3, 3A, 3B having layout data on the diffused parts only are inserted, deciding the data on the diffused parts can be made with only one-time chip layout. Accordingly, the circuit correction similar to the one in the gate array mode can be facilitated.