To provide a semiconductor integrated circuit and its power supply control method for reducing consumed power of a CPU domain in an operation mode.
An interruption power source control unit 5 monitors interruptions 11, 21, 31 from function blocks 1, 2, 3 and a power control command 41 from a CPU 4. When an interruption or a command is made, the control unit 5 performs power control in accordance with content of an interruption power control table 50. The control performs ON/OFF control of power switches 12, 22, 32, 42, and performs outputs of control signals 581, 582 to power source interruption countermeasure elements 81, 82. When the control supplies power to necessary blocks, the control unit 5 starts up the corresponding blocks in accordance with the table 50.
WO/2003/036450 | DRAM POWER MANAGEMENT |
JPH1139769 | INFORMATION PROCESSOR AND POWER SAVING DEVICE |
WO/2019/117623 | METHOD AND APPARATUS FOR OPERATING A PROCESSOR IN AN ELECTRONIC DEVICE |
JPH07141074A | 1995-06-02 | |||
JP2006107127A | 2006-04-20 | |||
JP2004021574A | 2004-01-22 | |||
JPH07287699A | 1995-10-31 | |||
JPH09160684A | 1997-06-20 | |||
JP2004140503A | 2004-05-13 |
Toshimitsu Ichikawa
Kimihide Hashimoto
Next Patent: IMAGE PROCESSOR AND IMAGE PROCESSING METHOD