To provide a method by which a plurality of memory circuits and other circuits in a semiconductor integrated circuit in which a plurality of the memory circuits and buses with which the memory circuits and other circuits are connected to each other are built are tested simultaneously.

If a test control signal 1 is set to a '1' state, addresses, data and control signals of a ROM 4 and a RAM 5 are generated by a test vector generating circuit 2 and addresses, data and control signals from a CPU 3 are released from the accesses of the ROM and the RAM. At that time, a random logic 6 can be accessed from the CPU 3 irrelevantly to the tests of the ROM and the RAM. On the other hand, the test results of the ROM and the RAM are simultaneously inputted to a circuit 7 for the signal compression of the output from the memory to subject the test results of the ROM and the RAM to the signal compression together. Thus, a plurality of memories such as ROM, RAM, etc., can be tested together and, further, other circuits can be tested simultaneously.