SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURE THEREOF

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURE THEREOF

Document Type and Number:

Japanese Patent JPH01290260

Kind Code:

A

Abstract:

PURPOSE: To prevent an overhang from occurring so as to restrain a disconnection completely by a method wherein a first electrode layer is provided around a contact hole of a Schottky barrier diode.

CONSTITUTION: A first insulating layer 3 deposited of a semiconductor substrate 1 and contact holes 4 and 5 of a circuit element formed by etching the first insulating layer 3 are provided. The contact hole 4 is used to bring elements other than a Schottky barrier diode 2 into an ohmic contact. A first electrode layer 7 formed of aluminum which contains Si is provided around a contact hole 6 of the Schottky barrier diode. By these processes, even if a layer metal of the first electrode layer 7 is subjected to a dry etching, an overhang is prevented from occurring around the contact hole 6, so that a disconnecting can be completely restrained.

More Like This:

WO/2024/048766	CRYSTAL, MULTILAYER STRUCTURE, ELEMENT, ELECTRONIC DEVICE, ELECTRONIC APPLIANCE, AND SYSTEM
JPH09213715	FIELD EFFECT TRANSISTOR AND MANUFACTURE THEREOF
JPH0513469	SEMICONDUCTOR DEVICE

Inventors:

NOMURA YOSHINOBU

Application Number:

JP12105588A

Publication Date:

November 22, 1989

Filing Date:

May 18, 1988

Export Citation:

Click for automatic bibliography generation Help

Assignee:

SANYO ELECTRIC CO

International Classes:

H01L29/872; H01L29/47; H01L29/861; (IPC1-7): H01L29/48; H01L29/91

Attorney, Agent or Firm:

Takuji Nishino (1 person outside)

Previous Patent: CLOSE CONTACT TYPE EQUI-MULTIPLYING SENSOR

Next Patent: MANUFACTURE OF GATE TURN OFF THYRISTER