To provide a semiconductor integrated circuit, which can measure accurately frequencies and jitters of the built-in PLL (phase locked loop), and measurement method for its jitters.

A master clock signal MCK obtained by N multiplication of an external clock signal ECK is generated at a PLL 10. The master clock signal MCK is given to a first input side of an AND 32, and gate control is conducted by an enable signal EN given to a second input side of the AND 32. The output side of the AND 32 is connected to a counter 34, and a count value of the counter 34 is outputted from an output terminal 36 to outside. Therefore, the PLL 10 is normal, if a count value of the counter 34 takes N×M when an enable signal EN having M cycle pulse-width of an external clock signal ECK is given to a control terminal 33.