Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND MEASUREMENT METHOD FOR ITS JITTER
Document Type and Number:
Japanese Patent JP3847150
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, which can measure accurately frequencies and jitters of the built-in PLL (phase locked loop), and measurement method for its jitters.
SOLUTION: A master clock signal MCK obtained by N multiplication of an external clock signal ECK is generated at a PLL 10. The master clock signal MCK is given to a first input side of an AND 32, and gate control is conducted by an enable signal EN given to a second input side of the AND 32. The output side of the AND 32 is connected to a counter 34, and a count value of the counter 34 is outputted from an output terminal 36 to outside. Therefore, the PLL 10 is normal, if a count value of the counter 34 takes N×M when an enable signal EN having M cycle pulse-width of an external clock signal ECK is given to a control terminal 33.
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Inventors:
Fumio Eguchi
Application Number:
JP2001361961A
Publication Date:
November 15, 2006
Filing Date:
November 28, 2001
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
G01R29/02; H03K21/02; G01R31/30; G01R31/317; G11C29/02; H03K21/40; H03L7/08; H03L7/18; (IPC1-7): H03K21/02; G01R29/02; H03K21/40; H03L7/08
Domestic Patent References:
| JP11023662A | ||||
| JP9005398A | ||||
| JP10288653A | ||||
| JP2002108491A |
Attorney, Agent or Firm:
Kakimoto Yasunari