SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND TESTING METHOD FOR SEMICONDUCTOR MEMORY DEVICE

Japanese Patent JP3857697

B2

PROBLEM TO BE SOLVED: To prevent an accident such that a large current is fed to common connecting wiring even when a driver is multiply selected.
SOLUTION: A data signal (datai) and selection signal (selecti) are input to each of basic unit circuits 2 which constitute a multiplicity-to-one multiplexer, and each of output terminals is connected to common connecting wiring 1. Each of the basic unit circuit comprises a disparity detection circuit 3 which detects status disparity between the common connecting wiring and the data signal, a control circuit 4 which controls drive timing of the common connecting wiring upon state transition of the selection signal, and a tristate buffer 7 which drives the common connecting wiring according to the state of the data signal when both output of the disparity detection circuit and the control circuit are in activated state, and otherwise maintains high impedance. The state of the common connecting wiring 1 is maintained by a state maintaining circuit 5 and output through an output buffer 6.

Toshimasa Yukikawa

JP2004087166A

December 13, 2006

March 24, 2004

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Toshiba Corporation

G01R31/28; G11C5/00; G11C7/10; G11C11/401; G11C29/00; G11C29/06; G11C29/34; H01L27/10; H03K5/00; H03K17/00; H03K17/16; (IPC1-7): G01R31/28; G11C11/401; G11C29/00; H03K5/00; H03K17/00; H03K17/16

JP4229500A

Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto

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