To provide a semiconductor integrated circuit containing a clock supply circuit, having no concerns about malfunction, to which clock gating technique has been applied.

The clock supply circuit uses a buffer tree composed of a plurality of buffers 101, and supplies a clock signal CLK to each flip-flop 104a-104d that is to serve a register. Clock gating circuits for applying enable logic 105 for controlling the supply of the clock signal CLK are duplicated for clock gating circuits 104a-104d, that equal in number to that of the flip-flops 104a-104d, these circuits are arranged so as to physically adjoin the flip-flops 104a-104d, and the output of each gating circuit 104a-104d is connected directly to each of flip-flops 104a-104d.