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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF INHIBITING DATA READ OPERATION OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND INTEGRATED CIRCUIT TYPE MEMORY MEDIUM
Document Type and Number:
Japanese Patent JP3967409
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which assures operation to protect data being stored.
SOLUTION: This circuit device includes a memory cell 5 having threshold value variable type memory elements M1 to Mn connected in series between the bit line potential supplying point D and the source potential supplying point S. When data is read from the memory cell 5, a voltage which makes a memory element M1 non-conductive is supplied to at least one of the memory elements M1 to Mn in order to inhibit read operation of data.


Inventors:
有留 誠一
Application Number:
JP1996000349036
Publication Date:
August 29, 2007
Filing Date:
December 26, 1996
Export Citation:
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Assignee:
株式会社東芝
International Classes:
G11C16/02; G11C8/20; G11C16/04; G11C16/22; G11C16/26; (IPC1-7): G11C16/02; G11C16/04
Domestic Patent References:
JP5325576A
JP7253932A
JP2230444A
JP59218689A
JP6251595A
JP7093223A
JP8077781A
Attorney, Agent or Firm:
鈴江 武彦
河野 哲
中村 誠
村松 貞男
橋本 良郎