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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION METHOD THEREFOR
Document Type and Number:
Japanese Patent JP2012243193
Kind Code:
A
Abstract:

To reduce a power source ripple at the time of switching from a low-power operation mode to a high-power operation mode.

A series regulator comprises a reference voltage generation circuit 10, an error amplifier 11, an output transistor 12, an output voltage dividing circuit 13, an operating current setting part 14 and a controller 15. The output transistor 12 includes first and second output transistors M1 and M2 that are connected in parallel between an input terminal Vin and an output terminal Vout. An element size of the first output transistor M1 is smaller than that of the second output transistor M2. The controller 15 in a low-power operation mode sets an operating current value at a small value I1 through control, and sets the first and second output transistors M1 and M2 to an active state and a non-active state through control, respectively. The controller 15 in a high-power operation mode sets the operating current value at a greater value I1+I2 through control, and sets both of the first and second output transistors M1 and M2 to the active state through control. The controller 15 instantaneously sets the operating current value at a much greater value I1+I2+I3 through control during a predetermined period t2 after a change from the low-power operation mode to the high-power operation mode.


Inventors:
IGARI TAKAYUKI
HORIUCHI TAKESHI
Application Number:
JP2011114638A
Publication Date:
December 10, 2012
Filing Date:
May 23, 2011
Export Citation:
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Assignee:
RENESAS ELECTRONICS CORP
International Classes:
G05F1/56
Attorney, Agent or Firm:
Shizuyo Tamamura