Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION METHOD THEREOF
Document Type and Number:
Japanese Patent JP2014192918
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To solve such a problem that a second digital signal has a phase lead ahead of a first digital signal due to failure, and a polyphase motor rotates reversely.SOLUTION: A semiconductor integrated circuit includes a reverse rotation prevention circuit 13 including an abnormal waveform period detection counter 1312 for forming motor drive output signals Mount1, 2 in response to digital signals Dout1, 2, and variable delay circuits 134, 137. When the Dout2 has a phase lead ahead of the Dout1 due to failure, the counter 1312 counts the phase difference of lead phase of rising between the lead phase side Dout2 and the lag phase side Dout1. The Dout 2 is supplied to the inputs of the variable delay circuits 134, 137, and a second motor drive output signal Mout2 for preventing reverse rotation of a motor is formed from the output of the variable delay circuits. The lag time between the Dout 2 at the input of the variable delay circuit and the Mout2 at the output of the variable delay circuits 134, 137 include at least the phase difference of lead phase counted by the counter 1312.
Inventors:
NISHINO TATSURO
Application Number:
JP2013063503A
Publication Date:
October 06, 2014
Filing Date:
March 26, 2013
Export Citation:
Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H02P8/38
Attorney, Agent or Firm:
Shizuyo Tamamura