Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND SCAN TEST METHOD THEREFOR
Document Type and Number:
Japanese Patent JP2017096881
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit with which it is possible to effectively reduce the required time of a scan test in a large-scale circuit using a multibit flip-flop.SOLUTION: A multibit flip-flop provided in the semiconductor integrated circuit includes, in an input front stage of a master latch 1a of a first stage (first bit), a selector 4a to which a scan shift signal SIN and a scan shift enable signal SEN are inputted, and also includes a selector 4c in an input front stage of a slave latch 2b of a next stage (second bit), not in an input front stage of a master latch 1b of a next stage (second bit), the selector 4c selecting, by the scan shift enable signal SEN, a data output M1I of the master latch 1a of the first stage and a data output M2I of the master latch 1b of the next stage and thereby switching between normal operation and scan shift operation. Thus, it is possible to cut down one cycle of high-going transition of a clock signal CLK during scan shift operation.SELECTED DRAWING: Figure 5
Inventors:
KONO MASAHARU
Application Number:
JP2015232087A
Publication Date:
June 01, 2017
Filing Date:
November 27, 2015
Export Citation:
Assignee:
RICOH CO LTD
International Classes:
H01L21/822; G01R31/28; H01L27/04
Attorney, Agent or Firm:
Takashi Satoru