Title:
SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR STORAGE DEVICE, AND MEMORY SYSTEM
Document Type and Number:
Japanese Patent JP2023040523
Kind Code:
A
Abstract:
To provide a semiconductor integrated circuit, a semiconductor storage device, and a memory system capable of improving measurement resolution of a pulse signal while suppressing an area and power consumption.SOLUTION: Included are: a delay line group 530 having a plurality of delay lines 53β which have a plurality of flip flops 531_β with a delay amount Tw serially connected; a delay element group 540 which generates a plurality of output clock signals having a smaller delay difference in a second delay amount than in the delay amount Tw; and a delay part 55 which is capable of setting a smaller third delay amount than the second delay amount. The delay element group 540 and the delay part 55 are serially connected together between an output terminal of an input signal CLK_DET and an input terminal of the delay line group 530.SELECTED DRAWING: Figure 6
Inventors:
NAKADA MASATSUGU
Application Number:
JP2021147559A
Publication Date:
March 23, 2023
Filing Date:
September 10, 2021
Export Citation:
Assignee:
KIOXIA CORP
International Classes:
G11C7/22; G06F12/00; G11C7/10; G11C16/04; G11C16/32; H03K5/05
Attorney, Agent or Firm:
Patent Attorney Corporation Itosin International Patent Office