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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST GENERATION PROGRAM
Document Type and Number:
Japanese Patent JP2004320433
Kind Code:
A
Abstract:

To provide a semiconductor integrated circuit and a test generation program for testing a buried core efficiently while separating a custom logic section and a buried core section in a semiconductor integrated circuit having a custom logic section and a buried core.

Between a buried core 11 and a custom logic section 12, a test shift register 13 constituting a scan path circuit for testing the buried core 11 of an input register and an output register is provided, and the first stage flip-flop of a scan path circuit 122 in the custom logic section 12 is connected with the last stage flip-flop of the test shift register 13.


Inventors:
HOSHI NAOYUKI
TANAKA JUNYA
Application Number:
JP2003111407A
Publication Date:
November 11, 2004
Filing Date:
April 16, 2003
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/82; H01L21/822; H01L27/04; H03K19/00; G01R31/28; (IPC1-7): H03K19/00; G01R31/28; H01L21/82; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Hiroaki Sakai