To insert a test circuit without having to change timing between a plurality of prescribed registers.

A semiconductor integrated circuit comprises a circuit block which forms partial paths (111-114); delay circuits (121-124); selection circuits (131-134); and a control circuit (140). The circuit block which forms the partial paths (111-114) is included in a signal path in which signals outputted from a first flip-flop (101) are inputted to a second flip-flop (102). The delay circuits (121-124) have delay characteristics equivalent to delay characteristics of when signals are transmitted through the partial paths and simulate the partial paths (111-114). The selection circuits (131-134) select and output either of output signals of the partial paths (111-114) or output signals of the delay circuits (121-124). The control circuit (140) controls signals selected by the selection circuits (131-134) during path delay fault testing for detecting path delay faults.