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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST METHOD THEREFOR
Document Type and Number:
Japanese Patent JPH08327699
Kind Code:
A
Abstract:

PURPOSE: To obtain a technology for ensuring the AC characteristics using an existing tester or an inexpensive tester even if the operating frequency and function of an LSI are enhanced.

CONSTITUTION: When the AC characteristics of an LSI are measured, signal from a control terminal 11 is set at 1 level. A control circuit 6 functions to establish a path from an input pin 3 through a critical path equivalent circuit 5 to an output pin 4. When a signal (of any frequency) varying from 1 to 0 (or from 0 to 1) is fed to the input pin 3, a signal appears at the output pin 4 while passing through the critical path equivalent circuit 5 with a time lag equivalent to the critical path of the circuit of actual product. Phase difference (time lag) between the signal appearing at the output pin 4 and the input signal is then measured and when the it is within an allowable range, the AC characteristics are satisfied and a decision is made that the LSI is acceptable.


Inventors:
YANO KOJI
Application Number:
JP13635795A
Publication Date:
December 13, 1996
Filing Date:
June 02, 1995
Export Citation:
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Assignee:
HITACHI LTD
HITACHI HOKKAI SEMICONDUCTOR
International Classes:
G11C29/00; G11C29/56; H01L21/822; H01L27/04; G01R31/28; (IPC1-7): G01R31/28; H01L27/04; H01L21/822
Attorney, Agent or Firm:
Ogawa Katsuo