To realize a testing function at the same speed as that in an actual use on a semiconductor integrated circuit by means of a comparatively low speed tester.

A PLL circuit 3 outputting clock signals by a fixed frequency according to a control signal from the outside, an inputting means 4 inputting an external clock signal B from the tester 6, and a switching means 5 between the external clock signal B from the tester 6 and the clock signal A from the PLL circuit are arranged inside the semiconductor integrated circuit, and in operation of a test, the clock signals A are supplied by a desired frequency from the PLL circuit 3 at the same speed as that in actual use.