To generate a stable internal clock signal in synchronism with the frequency of an external clock signal at a broad band, using a simple configuration and immune to an external disturbance.
A frequency identification circuit 2 receives an external clock signal extCLK received via a clock input buffer 1 of this semiconductor integrated circuit at its one input as a clock signal ECLK, and the frequency identification circuit 2 receives a basic clock signal BCLK generated by a basic clock oscillator 3 at the other input. The frequency identification circuit 2 counts a period (pulse) of the basic clock signal for a prescribed period of the external clock signal extCLK, and a digital controlled oscillator(DCO) 4 is oscillated on the basic of a count DCOIN and an internal clock signal ICLK is generated.
KIKUKAWA HIROHITO
Next Patent: HIGH FREQUENCY MODULATION TYPE PHASE-LOCKED LOOP CIRCUIT