SEMICONDUCTOR INTEGRATED CIRCUIT

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT

Document Type and Number:

Japanese Patent JP2009063519

Kind Code:

A

Abstract:

To provide a semiconductor integrated circuit capable of performing a two-pattern test and a one-pattern test, and shortening a time required for inspection, while suppressing increase of an occupied area.

This semiconductor integrated circuit has a first logic circuit, a second logic circuit, and a plurality of flip-flops arranged between the first logic circuit and the second logic circuit. Each flip-flop has a master selector for receiving output from the first logic circuit, a master latch for receiving output from the master selector, a slave selector for receiving output from the master latch, and a slave latch for receiving output from the slave selector and outputting it to the second logic circuit.

More Like This:

JPH05233003	SYSTEM CONTROLLED BY MANUALLY OPERABLE KEY
JP7130757	Integrated circuit margin measurement and failure prediction equipment
JP2003121499	SEMICONDUCTOR INTEGRATED CIRCUIT WITH BUILT-IN TEST FUNCTION, STORAGE MEDIUM FOR STORING ELECTRONIC DESIGN DATA COMPRISING TEST CODE GENERATION PROGRAM, TEST METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, TEST CODE GENERATION AUTOMATIZING METHOD AND ITS PROGRAM

Inventors:

KATO KENTARO
NANBA KAZUTERU
ITO HIDEO

Application Number:

JP2007233388A

Publication Date:

March 26, 2009

Filing Date:

September 07, 2007

Export Citation:

Click for automatic bibliography generation Help

Assignee:

UNIV CHIBA

International Classes:

G01R31/28; H01L21/822; H01L27/04

Previous Patent: SEMICONDUCTOR INTEGRATED CIRCUIT, AND INSPECTION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT

Next Patent: DEVICE AND METHOD FOR DISPLAYING ELECTRONIC MAP, AND MEDIUM STORING ELECTRONIC MAP DISPLAY PROGRAM