To solve the following problem: when a clock signal becomes a high frequency, a setup time cannot be secured among the clock signal CLK, a chip select signal CS that is a control signal, a read/write signal nRW and a byte write signal EN.

A semiconductor integrated circuit includes a clock signal generation circuit to which a first clock signal CLK and a chip select signal output based on an address are each input and which generates a first-clock-signal-based second clock signal RAMCLK after the lapse of a predetermined time from the input of the chip select signal.