Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2009212736
Kind Code:
A
Abstract:
To prevent deterioration in imprint characteristics of a ferroelectric capacitor in a semiconductor integrated circuit in which data signals of a latch circuit are held in the ferroelectric capacitor.
The semiconductor integrated circuit has a latch circuit 10 provided with a signal holding part 12 for holding data signals D, and ferroelectric capacitors F1, F2 electrically connected to the signal holding part 12 via switches TR1, TR2. Only during a prescribed period, the switches TR1, TR2 are turned on so as to hold a remanent polarization corresponding to potential of the data signal D in the ferroelectric capacitors F1, F2.
Inventors:
OGAWA KAZUYA
Application Number:
JP2008052769A
Publication Date:
September 17, 2009
Filing Date:
March 04, 2008
Export Citation:
Assignee:
FUJITSU MICROELECTRONICS LTD
International Classes:
H03K3/356; H03K3/037; H03K19/185; H03K23/40
Domestic Patent References:
| JP2004064557A | 2004-02-26 | |||
| JPH10133768A | 1998-05-22 | |||
| JPH04367120A | 1992-12-18 | |||
| JPH05242667A | 1993-09-21 | |||
| JPH10190416A | 1998-07-21 | |||
| JPH10303738A | 1998-11-13 | |||
| JPH118550A | 1999-01-12 | |||
| JPS63227119A | 1988-09-21 | |||
| JPH10133768A | 1998-05-22 | |||
| JP2003258626A | 2003-09-12 | |||
| JP2004064557A | 2004-02-26 |
Other References:
JPN6010070505; Ｖ．Ｓｔｏｊａｎｏｖｉｃ他: '「Ｃｏｍｐａｒａｔｉｖｅ Ａｎａｌｙｓｉｓ ｏｆ Ｍａｓｔｅｒ-Ｓｌａｖｅ Ｌａｔｃｈｅｓ ａｎｄ Ｆｌｉｐ-Ｆｌｏｐｓ ｆｏｒ Ｈｉｇｈ-Ｐｅｒｆｏｒｍａｎｃｅ ａｎｄ Ｌｏｗ-Ｐｏｗｅｒ Ｓｙｓ' ＩＥＥＥ ＪＯＵＲＮＡＬ ＯＦ ＳＯＬＩＤ-ＳＴＡＴＥ ＣＩＲＣＵＩＴＳ ＶＯＬ．３４， ＮＯ．４, 199904, ｐｐ５３６-５４８, ＩＥＥＥ
Attorney, Agent or Firm:
Keizo Okamoto
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