Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2016036109
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that can suppress a voltage drop and noise.SOLUTION: A semiconductor integrated circuit includes an output circuit, a noise extraction circuit, a noise cancellation signal generation circuit, a delay circuit, and a superimposing circuit. The output circuit generates a predetermined output voltage according to an input voltage. The noise extraction circuit extracts a noise component signal contained in the input voltage. The noise cancellation signal generation circuit generates a noise cancellation signal that is obtained by adjusting the voltage level of the noise component signal according to the voltage level of the input voltage. The delay circuit adjusts a timing at which the noise cancellation signal generation circuit generates the noise cancellation signal. The superimposing circuit superimposes the noise cancellation signal on the output voltage.SELECTED DRAWING: Figure 1
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Inventors:
OSADA KAZUYA
Application Number:
JP2014158931A
Publication Date:
March 17, 2016
Filing Date:
August 04, 2014
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H04B15/00; H03K5/1252
Attorney, Agent or Firm:
Hirohito Katsunuma
Takeshi Sekine
Akaoka Akira
Yasushi Kawasaki
Takeshi Sekine
Akaoka Akira
Yasushi Kawasaki