Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2016178183
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which increase in delay time can be suppressed.SOLUTION: A semiconductor integrated circuit according to the present embodiment comprises a plurality of lines of input wiring, a plurality of lines of output wiring, and a memory part having a memory cell array. The memory cell array comprises: a plurality of lines of first wiring provided so as to correspond to the plurality of lines of input wiring; a plurality of lines of second wiring intersecting the plurality of lines of first wiring and provided so as to correspond to the plurality of lines of output wiring; and a plurality of sub cell arrays each including a memory element which is provided in an intersection region of some of the plurality of lines of first wiring and some of the plurality of lines of second wiring and which has first and second terminals, the first terminal of each memory element being connected with corresponding one of the some lines of first wiring, the second terminal of each memory element being connected with corresponding one of the some lines of second wiring. The plurality of sub cell arrays are connected with the lines of output wiring different from each other.SELECTED DRAWING: Figure 6
Inventors:
MATSUMOTO MARI
YASUDA SHINICHI
YASUDA SHINICHI
Application Number:
JP2015056340A
Publication Date:
October 06, 2016
Filing Date:
March 19, 2015
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H01L21/82; H01L21/822; H01L27/04; H03K19/173; H03K19/177
Attorney, Agent or Firm:
Hirohito Katsunuma
Takeshi Sekine
Suzuki Junsei
Takeshi Sekine
Suzuki Junsei
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