Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2567163
Kind Code:
B2
Abstract:
PURPOSE: To obtain an original oscillating output with less noise or without noise generated from a frequency divider circuit by stopping the frequency divider circuit when the original oscillation output is extracted from an oscillation circuit.
CONSTITUTION: When an original oscillating frequency signal is selected by a clocked inverter(CI) 1, the output C of a decoder 10 goes to an H level. Outputs D, E, F go to an L level on the other hand and since only the CI1 is operated as the usual inverter, an original oscillation frequency signal is outputted. Then the H level of the output C of the decoder 10 and a signal H level from an oscillation stop terminal 13 via inverters 15, 18 are inputted to a NAND circuit 21, from which an L level signal is inputted to the reset terminal R of a frequency divider circuit 9 to be stopped. Thus, when the original oscillation frequency signal is extracted from a terminal 12 as an output signal, the operation of the circuit 9 is stopped and no switching noise is present on the circuit, then the power supply is made stable. Thus, the noise in the original oscillation output is almost lost and a malfunction due to noise is eliminated.
Inventors:
ITO TAKAHIRO
INOE TOSHIHISA
INOE TOSHIHISA
Application Number:
JP21847691A
Publication Date:
December 25, 1996
Filing Date:
August 29, 1991
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/8238; G06F1/04; G06F1/06; H01L27/092; H03B19/00; H03K3/03; H03K23/66; (IPC1-7): H03K3/03; H01L21/8238; H01L27/092
Domestic Patent References:
| JP5429956A | ||||
| JP1319323A |
Attorney, Agent or Firm:
Takehiko Suzue