Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3239023
Kind Code:
B2
Abstract:
PURPOSE: To prevent application of a voltage over the a permissible range to the integrated circuit by an N-channel path transistor(TR) between an input output terminal of a low voltage IC and the integrated circuit and applying a required potential to its gate.
CONSTITUTION: An N channel path TR 7 is provided between an input output terminal 3 of a low voltage semiconductor integrated circuit and input output circuits 1, 2 or the like and a voltage equal to a power supply voltage Vcc2 is applied to a gate of the path TR 7. A power supply voltage Vcc1 of other consecutive semiconductor integrated circuit 4 is, e.g. 5.0V. Though the input voltage Vin fed to the input terminal 3 is 5.0V, a maximum voltage applied to input TRs 10, 11 or the like is as lower as Vcc2-Vt, where the Vt is a threshold voltage of the path TR, e.g. to be Vt=0.5V. Let a power supply voltage of a low voltage IC be Vcc2=3.3V, then the voltage applied to the input TRs 10, 11 or the like is 2.8V. The Vp is selected to be a proper voltage in excess of the Vcc2 to reduce the input output impedance.
Inventors:
Junichi Matsuda
Isamu Kurihara
Isamu Kurihara
Application Number:
JP22819094A
Publication Date:
December 17, 2001
Filing Date:
September 22, 1994
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
H03K19/003; H03F1/52; H03K17/00; H03K17/687; H03K19/007; H03K19/0175; (IPC1-7): H03K17/00; H03K17/687; H03K19/003; H03K19/0175
Domestic Patent References:
| JP4243321A | ||||
| JP799437A | ||||
| JP897703A | ||||
| JP865135A |
Attorney, Agent or Firm:
Masamasa Shibano