Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3243828
Kind Code:
B2
Abstract:
PURPOSE: To decrease the electric charge of switch control signal of large load in quantity so as to lessen a semiconductor integrated circuit in power consumption by a method wherein switch control signal which used to be pre-charged up to a potential higher than that of an inner power supply is pre-charged to the potential of an inner power supply.
CONSTITUTION: Switch control signals SW1 and SW2 are connected to P channel transistors 112 and 113 whose sources are connected to a VPP level, N channel transistors 114 and 115 whose sources are connected to a ground level, and N channel transistors 116 and 117 whose sources are connected to a VCC level, and the gates of these transistors are controlled by three-level output signals. Switch control signals are pre-charged to a VPP level on standby, only switch control signals on a selection memory block side are set to a VPP level at memory access, and switch control signals on a non-selection memory block side are set to a ground level. By this setup, the electric charge of switch control signal of large load can be lessened in quantity.
Inventors:
Toshikazu Suzuki
Hiroyuki Yamauchi
Hiroyuki Yamauchi
Application Number:
JP9761392A
Publication Date:
January 07, 2002
Filing Date:
April 17, 1992
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G11C11/417; G11C11/401; G11C11/407; G11C11/409; G11C16/06; G11C17/00; H01L27/10; (IPC1-7): G11C11/409
Domestic Patent References:
| JP5210968A | ||||
| JP562463A | ||||
| JP5258577A |
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)