SEMICONDUCTOR INTEGRATED CIRCUIT

Japanese Patent JP3251421

B2

PURPOSE: To obtain the semiconductor integrated circuit which performs arithmetic processing using two-dimensional data at a high speed with high parallelism. CONSTITUTION: This semiconductor integrated circuit is equipped with a two-dimensional memory array MAR, a parallel data transfer circuit TRC which transfers data read out in parallel through data lines by selecting word lines of the two-dimensional memory array MAR to an arithmetic circuit group PE in parallel, and the arithmetic circuit group PE which performs arithmetic processing in parallel by using the data transferred from the parallel data transfer circuit TRC; and the individual arithmetic circuits PE can access plural successive word lines and data lines of the two-dimensional memory array MAR through the parallel data transfer circuit TRC, and the ranges of data lines of the two-dimensional memory array MAR that plural adjacent arithmetic circuits PE can access overlap with each other. Thus, the ranges of the data lines that the adjacent arithmetic circuits PE can access overlap with each other, so convolution arithmetic, etc., can be performed in parallel for two-dimensional data stored in the two-dimensional memory array MAR.

Takao Watanabe
Yoshinobu Nakagome
Kazuo Ishikura
Tetsuya Nakagawa
Atsushi Kiuchi

JP7182194A

January 28, 2002

April 11, 1994

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株式会社日立製作所

G06T1/20; G06F13/00; G06F15/167; G06F15/80; G06F17/10; G06F17/15; G06T5/20; G11C7/10; (IPC1-7): G06T1/20; G06T5/20

JP683787A
JP6175956A
JP61117665A
JP3106283A
JP453389A
JP5268593A

Yasuo Sakuta (1 outside)

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