Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP3981373
Kind Code:
B2
Abstract:
To form CPUs with various kinds of bit widths necessary for executing an object program generated so as to reduce power consumption of a semiconductor integrated circuit by increasing use efficiency of the CPUs into a semiconductor integrated circuit equipped with a programmable device.
In this semiconductor integrated circuit 1 equipped with the programmable device 11 having a rewritable circuit structure, a control part 12 forms, in the programmable device 11, a circuit comprising the CPUs 14 of designated bit widths and of a designated quantity, and buses 17 and 18 connected to them.
COPYRIGHT: (C)2005,JPO&NCIPI
Inventors:
Hou Houba
Shuichi Takayama
Junichi Yano
Hisato Yoshida
Katsuyuki Imamura
Junichi Mori
Junya Yamamoto
Shuichi Takayama
Junichi Yano
Hisato Yoshida
Katsuyuki Imamura
Junichi Mori
Junya Yamamoto
Application Number:
JP2004250861A
Publication Date:
September 26, 2007
Filing Date:
August 30, 2004
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F9/30; G06F15/80; G06F12/00; G06F12/06; G06F13/16; H03K19/173
Domestic Patent References:
| JP2000181566A | ||||
| JP2000311156A |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori