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Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP3991802
Kind Code:
B2
Abstract:

To reduce an area of a semiconductor integrated circuit that has a function of holding a history of data by each bit when a plurality of signals are continuously output based on multi-bit data.

This semiconductor integrated circuit comprises a plurality of groups of half latch circuits HL1-HL5 that hold the history of the data having the plurality of bits by each bit by outputting input data when a clock signal is in a first level and hold output data when the clock signal is in a second level, a clock signal supplying circuit 10 for supplying one group of clock signals to each group of half latch circuits in order to sequentially shift the data held in the each group of the half latch circuits, and a plurality of control circuits 13 for controls each of the characteristics of the signals to be output based on the history of the data held in the plurality of groups of half latch circuits.

COPYRIGHT: (C)2004,JPO


Inventors:
Hiroki Wachi
Application Number:
JP2002213364A
Publication Date:
October 17, 2007
Filing Date:
July 23, 2002
Export Citation:
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Assignee:
Seiko Epson Corporation
International Classes:
B41J2/36; H03K3/356
Domestic Patent References:
JP10026960A
JP11250682A
Attorney, Agent or Firm:
Mutsumi Yanase
Masaaki Utsunomiya
Atsushi Watanabe