Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP4458699
Kind Code:
B2
Abstract:
A semiconductor integrated circuit includes a first address transition detecting circuit which detects transitions of a row address signal and a column address signal of a memory cell array, a second address transition detecting circuit which detects only the transition of the column address signal, a control circuit which generates an internal circuit control signal with a desired period of time required for row access based on only a first detection signal and generates a column-related circuit control signal with a desired period of time required for column access to the memory cell array based on only a second detection signal, and a mode discriminator which determines one of the row access and the column access to be made and performs the access control operation based on the determination result.
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Inventors:
Yoshiaki Takeuchi
Application Number:
JP2001062268A
Publication Date:
April 28, 2010
Filing Date:
March 06, 2001
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C8/18; G11C11/403; G11C11/22; G11C11/401; H03K21/10
Domestic Patent References:
| JP845283A | ||||
| JP2005108301A |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai