To make low power consumption compatible with a high speed operation, particularly in a D flip-flop circuit having been contradictory in prior arts.

A semiconductor integrated circuit includes: a latch circuit A1 for receiving an input data signal D, a clock signal CK and first and second feedback signals S01, S02 and providing an output of an output data signal Q; a data retaining circuit A2 for retaining the output data signal NQ; and a feedback circuit A3 for receiving the input data signal D and the output data signal NQ and generating the first and second feedback signals S01, S02 based on logic combinations of the input data signal D and the output data signal NQ, and an internal operation of the latch circuit A1 is turned on/off by means of the first and second feedback signals S01, S02.

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