Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP7004038
Kind Code:
B2
Abstract:
To reduce a space of a standard cell to realize a circuit that drives a plurality of complementary transistor pairs in phase.SOLUTION: A multi-height standard cell of a semiconductor integrated circuit includes first and third regions of a first conductive type and second and fourth regions of a second conductive type. The first and second regions are arranged between a first power line and a second power line. The third and fourth regions are arranged between the second power line and a third power line. First and second gate electrodes have a linear shape in a gate layer and overlap the first to fourth regions. A third gate electrode overlaps the first region and the second region. The cell length of the multi-height standard cell is a distance between the center of the first power line and the center of the third power line in the second direction, which is M (M≥2) times the distance between the center of the first power line and the center of the second power line.SELECTED DRAWING: Figure 4
Inventors:
Yoshinori Tanaka
Application Number:
JP2020127193A
Publication Date:
January 21, 2022
Filing Date:
July 28, 2020
Export Citation:
Assignee:
Sony Group Corporation
International Classes:
H01L21/82; H01L21/822; H01L21/8238; H01L27/04; H01L27/092
Domestic Patent References:
| JP49111589A | ||||
| JP54116186A | ||||
| JP2001506429A |
Foreign References:
| US20090212327 |
Attorney, Agent or Firm:
Yasuhiro Iijima
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