Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH01187968
Kind Code:
A
Abstract:
PURPOSE:To measure even the gate delay time per one stage shortened easily by measurement only by an LSI tester by mounting a ring oscillator formed while having a specified logic gate and a frequency divider frequency-dividing an output of the ring oscillator. CONSTITUTION:A ring oscillator, at least one input side terminal of which is connected to an input terminal 2 for a semiconductor integrated circuit and which is shaped while having a specified logic gate, and a frequency divider 4 frequency-dividing an output from the ring oscillator and being formed so as to output a fixed frequency-dividing output from an output terminal 3 for the semiconductor integrated circuit are installed. NAND circuits 1-1,..., 1-n (n represents an odd number), the input terminal 2, the output terminal 3 and the frequency divider 4 are set up. When the frequency-dividing ratio of the frequency divider 4 is represented by 1/2, the delay time T until an output of the frequency divider 4 is inverted after a signal at a 'HIGH' level is added to the input terminal 2 is measured by an LSI tester, thus acquiring the delay time t0 per one stage of the NAND circuits 1-1,...,1-n by t0=(T/2).n.
Inventors:
IKEGAMI FUMIO
Application Number:
JP1300688A
Publication Date:
July 27, 1989
Filing Date:
January 22, 1988
Export Citation:
Assignee:
NEC CORP
International Classes:
H01L21/66; H01L21/822; H01L27/04; H03B5/42; H03K23/00; G01R31/28; (IPC1-7): G01R31/28; H01L21/66; H01L27/04; H03B5/42; H03K23/00
Attorney, Agent or Firm:
Shin Uchihara