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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH03225952
Kind Code:
A
Abstract:

PURPOSE: To enhance an electrostatic-breakdown resistant property without obstructing a high integration by a method wherein a protective circuit for an input circuit or an output circuit is formed of a second MOS field-effect transistor and other circuits are constituted of a first MOS field-effect transistor.

CONSTITUTION: A first MOS transistor 21 and a second MOS transistor 22 are formed on the same semiconductor substrate 23 composed of P-type silicon. When a surge voltage is applied to an output terminal 43 and it exceeds a drain breakdown strength of a transistor 44 for protection use, an electric current flows to the transistor 44 for protection use and an output transistor 41 is protected. Generally, a drain breakdown strength of the second MOS transistor 21 is lower than that of the first MOS transistor 21, and the second MOS transistor does not have a high-resistance region of an N- layer. As a result, even when an electric current flows, the second MOS transistor has a property that its thermal destruction is hardly caused, and it is suitable for the transistor 44 for protection use. On the other hand, since the output transistor 41 and its control circuit 42 are formed of the first MOS transistor 21, a high integration can be realized.


Inventors:
HASHIMOTO TAKASHI
YAMAZAKI HARUJI
Application Number:
JP2239490A
Publication Date:
October 04, 1991
Filing Date:
January 31, 1990
Export Citation:
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Assignee:
SANYO ELECTRIC CO
International Classes:
H01L29/78; H01L21/8234; H01L27/088; (IPC1-7): H01L27/088; H01L29/784
Attorney, Agent or Firm:
Koji Yasutomi (1 person outside)



 
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