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Document Type and Number:
Japanese Patent JPH0323712
Kind Code:

PURPOSE: To suppress ringing and also, to obtain VOH and VOL margins by inserting a resistor with a comparatively large resistance value between an output transistor and an output terminal, and providing a switching element to bias the resistor with certain delay time.

CONSTITUTION: The resistor with the comparatively large resistance value is inserted between the output transistors TR1, TR2 and the output terminal, and an N-channel MOS transistor TR3 is provided in parallel with the resistor. And the output of a NOR gate 8 setting a node A and a node B as two input is connected to the gate of the N-channel MOS transistor TR3 connected in parallel with the resistor via delay circuits 5-7. Thereby, the output of the transistor TR1 or TR2 goes to 'H' via the resistor R when it is energized, however, at this time, the rise of the output is moderated since it passes through the resistor R, thereby, the ringing is suppressed. When a node C goes to 'H' with certain delay, the transistor TR3 is energized, and the resistor R is bypassed after a time t3, therefore, a final level of 'L' goes to almost 0V.

Ozaki, Hideyuki
Application Number:
Publication Date:
January 31, 1991
Filing Date:
June 20, 1989
Export Citation:
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International Classes:
H03K17/16; G11C11/409; H03K19/0175; H03K19/0185; (IPC1-7): H03K17/16; H03K19/0175; H03K19/0185