PURPOSE: To detect a malfunction by itself by providing plural FFs, plural parallel transistors(TRs) switched by the output of the FFs and resistive elements connected in series to the device.

CONSTITUTION: When the circuit is normally in operation, only one of output terminals Q1-Q3 of FFs 1-3 goes to an H level. Malfunction takes place due to any cause and the two output terminals Q2, Q3 go to H, then N-channel TRs 2,3 are turned on. Then a voltage VB proportional to a ratio of the total ON-resistance to an ON-resistance of a P-channel TR 4 is outputted to a signal line 7. A threshold voltage VT of a NAND gate 5 is set to a relation of VA> VT>VB (VA is a resistance ratio of TRs 2, 4), and when two FFs or over go to H at malfunction, a reset signal is outputted to a signal line 8. As a result, a ring counter circuit is initialized and when a terminal IR connects to an interrupt generating circuit, the malfunction of the ring counter circuit is informed to a CPU.