PURPOSE: To prevent malfunction of 1/10, 1/11 frequency division by providing two NOR circuits, three D flip-flop circuits and one T flip-flop circuit to the semiconductor integrated circuit and applying an input signal to be fetched to the T flip-flop circuit from a Q output of a 2nd D flip-flop circuit.

CONSTITUTION: When a switching signal from a switching terminal 9 is set to a high level to prevent a Q output of a T flip-flop circuit FF 7 from being fetched to a NOR circuit 1, an output of a circuit 1 goes to an L level and an output of a NOR circuit 2 follows an output of a D flip-flop circuit FF 5. On the other hand, D FFs 4-6 implement 1/5 frequency division and the FF 7 implements 1/10 frequency division by an output of the FF 5. In the case of 1/11 frequency division, when the switching signal is set to an L level, the circuit 1 depends on the inverting output of the FF 7 and when the output is logical H, the circuit 2 cannot read a noninverting output of the FF 5 and the FFs 4-6 implement 1/6 frequency division. Conversely, when the output of the circuit 1 is at an L level, the output of the circuit 2 follows the output of the FF 5 and the FFs 4-6 implement 1/5 frequency division. Thus, a delay margin of the circuit 1 is equivalent to three clocks and malfunction of both 1/10 and 1/11 frequency division operations is prevented.