PURPOSE: To quicken an access time and to reduce a penetration current by interrupting a transistor route constituting a buffer circuit with a second control signal synchronous with a first control signal controlling an equalizing means.
CONSTITUTION: A transistor 12 between an output transistor 4 of a power source side and an output transistor 5 of a GND side is made nonconductive and the route is interrupted during an interval when a first and a second input nodes 18, 19 of a buffer circuit driving a data output terminal 6 are equalized and become intermediate potential. Thus, the route from a power source node 20 to the power source node 21 is interrupted and the penetration current does not flow even when the transistors 4, 5 constituting the buffer circuit are a slightly conductive state while making the access time a high speed. Thus, the access time is quickened and the penetration current is prevented and power consumption is reduced.
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SHIOMI TORU
HIGASHIDE YOSHIKO
OKAMOTO YASUYUKI
