PURPOSE: To obtain a stable circuit operation by providing a clock output terminal to a delay flip-flop.

CONSTITUTION: A delay flip-flop D-FF latches data inputted to a data input terminal at the rising of a clock signal inputted to a clock input terminal TI and through-outputs the inputted clock from a clock output terminal TO. Thus, data Din entering a 1st stage D-FF1a are being outputted sequentially toward a final stage D-FF in a shift register circuit at the rising of a clock Tin inputted to a final stage D-FF12 and outputted as data Y from an output terminal Q of a final stage D-FF1z. When the clock Tin is inputted to the final stage D-FF1z, a pre-stage D-FF receives and is operated by the clock via a post-stage D-FF and the change in the clock at the post-stage D-FF is faster than that of the pre-stage.