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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH05333955
Kind Code:
A
Abstract:

PURPOSE: To reduce the power consumption by stopping the drive of the logic circuit which inputs a clock to a dividing circuit based on a reset signal or the clock stop signal supplied from the outside.

CONSTITUTION: A logic circuit 1 works based on a clock signal and inputs a clock to a dividing circuit 2 which divides and outputs the clock. The circuit 2 stops its operation with input of a reset signal 3 and also stops its operation in a reset state when the signal 3 is inputted to the circuit 1. Therefore, the circuit 1 does not work despite the change of the signal 4 so that the power consumption of the circuit 1 can be suppressed.


Inventors:
KAWAKAMI YASUSHI
Application Number:
JP13723192A
Publication Date:
December 17, 1993
Filing Date:
May 28, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F1/04; (IPC1-7): G06F1/04
Domestic Patent References:
JPH04105108A1992-04-07
JP58101233B
JPS62191910A1987-08-22
JPS60154709A1985-08-14
Attorney, Agent or Firm:
Sugano Naka



 
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