SEMICONDUCTOR INTEGRATED CIRCUIT - NIPPON ELECTRIC IC MICROCOMPUT

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT

Document Type and Number:

Japanese Patent JPH0548023

Kind Code:

A

Abstract:

PURPOSE: To enable either a pull-up resistance or a pull-down resistance to be selected arbitrarily by applying an external control signal to both gates of a P-channel MOS transistor and an N-channel MOS transistor.

CONSTITUTION: When a control voltage which is fed to an external control terminal 51 is at a same potential as a power supply voltage VDD, a P-channel MOS transistor 1 is in OFF state and an N-channel MOS transistor is in ON state, thus forming a circuit showing a pull-down resistor. Then, when a control voltage which is fed to the external control terminal 51 is at a same potential as a grounding potential, the P-channel MOS transistor 1 is in ON state and the N-channel MOS transistor 2 is in OFF state, thus forming a circuit showing a pull-up resistor. When the external control terminal 51 is in open state. the P-channel MOS transistor is in ON state, thus forming a circuit showing a pull-up resistor. Therefore, either the pull-up resistor or the pull-down resistor can be selected arbitrarily.

Inventors:

YOSHIDA KAZUHIRO

Application Number:

JP19758591A

Publication Date:

February 26, 1993

Filing Date:

August 07, 1991

Export Citation:

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Assignee:

NIPPON ELECTRIC IC MICROCOMPUT

International Classes:

H01L21/8238; H01L27/092; (IPC1-7): H01L27/092

Attorney, Agent or Firm:

Uchihara Shin

Next Patent: JPS548024