PURPOSE: To simplify the circuit configuration in a parallel - serial conversion circuit and to reduce cost by reduction in the number of components and in a chip-occupied area.

CONSTITUTION: Parallel data D0-D7 are inputted to a latch circuit group 11 and stored tentatively and data stored tentatively are inputted to a clocked inverter group 28 provided corresponding to a latch circuit group 11. Data '1' are sequentially in a shift register 29 and an output of each bit is fed to a clock input terminal of clocked inverters 280-287 to control the active state sequentially thereby providing an output of serial data DS from the clocked inverter group 28. Furthermore, the integrated circuit is provided with a logic circuit 30 outputting a clock signal CK' for a period from start of output of the serial data SD till the output end based on an output of a most significant bit of the shift register 29. Through the constitution above, the logic circuit ancillary to the shift register is simplified and no binary counter is required.