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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0684913
Kind Code:
A
Abstract:

PURPOSE: To eliminate cross talk between adjacent wiring and prevent noise by permitting at least one layer of metal wiring to have a structure that covers almost whole plane of a substrate except an opening that introduces the top and bottom layer connecting parts and connecting the layer with power source or ground potential.

CONSTITUTION: First layers 2, 3 and 4 are arranged on a substrate 1. Then, second layer 5 is arranged on the layers 2, 3 and 4 and a third layer 7 is arranged at the top. The second layer 5 connected with a diffused layer 9 covers the whole plane of the substrate 1 except an opening 10 for introducing the connection of the first layer 3, which is connected with the diffused layer 8, with the third layer 7 and is connected with ground potential. Therefore, the diffused layer 9 is permitted to have ground potential. Thus, the first layer 2 and the third layer 7 are shielded by the second layer 5 and cross talk between a top layer wiring signal and a bottom layer wiring signal is eliminated. As a result, noise of the adjacent wiring signals is prevented.


Inventors:
YAMADA SUKETAKA
Application Number:
JP23218592A
Publication Date:
March 25, 1994
Filing Date:
August 31, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/82; H01L21/3205; H01L21/768; H01L21/822; H01L23/52; H01L23/522; H01L27/04; (IPC1-7): H01L21/3205; H01L21/82; H01L21/90; H01L27/04
Attorney, Agent or Firm:
Naotaka Ide