To constitute a test circuit which can efficiently test a memory without increasing terminals for test in a semiconductor integrated circuit including plural memories.

An address signal TAD, a data signal TDT and a control signal TRW for the same test are given to RAMs 14a, 14b through an input terminal Y of selectors 13a, 13b at the time of a memory test. Therefore, the same data is written in plural RAMs 14a and the like. It is discriminated whether all bits are 'H' or 'L' in output signals S14a, S14b of RAMs 14a, 14b by a comparing circuit 16. One bit in the output signal S14a of the RAM 14a and a comparison signal, CMP are outputted respectively from output terminals 18a, 18b. A test for the RAM 14a and the like can be performed by writing successively data of all 'H' or all 'L' as the data signal TDT and reading out them.