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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH10213631
Kind Code:
A
Abstract:

To remove a malfunctioned product in the test of a semiconductor integrated circuit without increasing the number of its terminals by a method wherein a transfer-gate switch means connects a voltage generation means to an external input terminal so as to be set to continuity in the test.

A transfer-gate switch AW1 is turned on so as to be changed over to a route used in a test. When a node N1 at a voltage generation means 1 is disconnected from the noninverting terminal (+) of a differential circuit Z1 at an internal circuit 2, the gate-electrode formation part of a transistor is set forcibly to an H-level. Since the differential circuit Z1 always continues to output the H-level, a H-type transistor at an inverter 11 is always turned off, and it cannot drive the input of a latch circuit 22 to the H-level. An oscillation output signal SO is not changed to the H-level. The oscillation output signal SO remains at an L-level so as not to be changed, and an oscillation is stopped. Consequently, when the stop of the oscillation of the internal circuit 2 is confirmed in the test of an IC, it is possible to detect the disconnection between the voltage generation means 1 and the internal circuit 2.


Inventors:
TOKUE TATSUYA
Application Number:
JP1510497A
Publication Date:
August 11, 1998
Filing Date:
January 29, 1997
Export Citation:
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Assignee:
NEC CORP
International Classes:
G05F3/24; G11C11/413; H03K3/0231; H03K19/00; G01R31/28; (IPC1-7): G01R31/28; G05F3/24; G11C11/413; H03K3/0231; H03K19/00
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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