To prevent output signals of two counters from interfering, even when the frequencies of output signals of the two counters are identical by providing a phase control means that controls 1st and 2nd counters frequency- dividing a same signal, so that phases of their output signals do not in match with each other.

Reference counters 49, 50 apply frequency division to an output signal S1 of a crystal oscillator 1. The counter 49 is provided with a 3-input AND circuit which is a component of a reference signal supply means that provides an output of a reference signal REF to inform its reset timing to the counter 50. The counter 50 is provided with a reset control means, consisting of an inverter and a 2-input OR circuit. When a phase of an output signal S49 of the counter 49 and a phase of an output signal S50 of the counter 50 match with each other, the reference signal REF is set to an L-level for a prescribed cycles. The output signal S50 of the counter 50 keeps an H-level in this cycle.