To reduce a delay difference between clock signals at different frequencies without expansion by arranging a variable delay circuit, with which the phase difference of a reference clock signal and a clock signal supply source clock signal is matched, at the clock signal supply source of a clock signal system except for a reference clock signal system.

A clock frequency divider 2 of an LSI chip 1 receives a source clock signal S and generates clock signals A-D at different frequencies. A clock the tree 4 adjusts clock skew while receiving the correspondent clock signals B-D outputted from a variable delay circuit 3. The variable delay circuit 3 defines a clock signal A' to be the terminating clock signal of the clock signal system, to which the clock signal A at the lowest frequency is supplied, as the reference clock signal, compares the phases of the reference clock signal A' and terminating clock signals B'-D', matches the phase difference of the reference clock signal and the clock signals B-D and regulates the delay difference between signals into sufficiently small value.