Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH1125201
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To make it possible to operate a highly accurate analog current product by finding out an weighted mean sum of two input currents at a floating point, generating voltage having a term of the product and exponentially converting the voltage to obtain a product of two current values. SOLUTION: Signal currents Ix, Iy from 1st and 2nd input signal current sources 1, 2 are logarithmically converted into voltage values Vx, Vy by NMOS transistors(TRs) 6 to 9 having sub-threshold operation. The potential level Vf of a floating point becomes a voltage value obtained by the weighted mean sum of capacity coupling by 1st and 2nd capacity means 10, 11. When capacity values Cx, Cy are equally set up, a product Ix.Iy of the input currents Ix, Iy is generated. The potential level Vf of the floating point is the gate-source voltage of an NMOS TR 12, and when a drain current is set up as Iout, the linear product Ix.Iy of the input currents Ix, Iy can be extracted as Iout=Ix.Iy.
Inventors:
OGAWA KATSUHISA
OMI TADAHIRO
SHIBATA SUNAO
OMI TADAHIRO
SHIBATA SUNAO
Application Number:
JP17686697A
Publication Date:
January 29, 1999
Filing Date:
July 02, 1997
Export Citation:
Assignee:
OMI TADAHIRO
CANON KK
CANON KK
International Classes:
G06G7/16; G06G7/163; (IPC1-7): G06G7/16
Attorney, Agent or Firm:
Yamashita
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