Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5969945
Kind Code:
A
Abstract:
PURPOSE:To wire each field-effect transistor easily, and to increase the degree of integration by forming a plurality of the FETs on a high-resistance substrate while forming a groove in depth reaching the high-resistance substrate between the adjacent two FETs and burying the groove with an insulator. CONSTITUTION:The comparatively deep groove can be formed to a compound semiconductor, particularly, a GaAs substrate, by a reactive-dry-etcher having a parallel plate electrode using CCl4 gas or CCl2F2 gas, the groove is buried with a polyimide group resin to flatten the surface, and each FET is wired by aluminum. There are methods of two kinds as a process for forming the groove. In a first method, a resist 9 is applied, the groove 7 is formed through reactive-ion- etching while using the resist as a mask and the polyimide group resin is applied or Si3N4 8 is deposited through plasma CVD. The whole surface is etched by the reactive-ion-etcher, the insulating film 8 on an active layer is brought to several thousands Angstrom thickness, and the process is shifted to a process for forming the electrode of the FET.
Inventors:
KANAZAWA KUNIHIKO
SHIMANO AKIO
NANBU SHIYUUTAROU
SHIMANO AKIO
NANBU SHIYUUTAROU
Application Number:
JP18072782A
Publication Date:
April 20, 1984
Filing Date:
October 14, 1982
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/76; H01L21/331; H01L21/762; H01L29/73; (IPC1-7): H01L27/08
Attorney, Agent or Firm:
Toshio Nakao