Title:
半導体集積回路、及び、同半導体集積回路を備えた装置
Document Type and Number:
Japanese Patent JP7173833
Kind Code:
B2
Abstract:
To allow for changing an operation frequency of an internal circuit at a high resolution without depending on PLL performance.SOLUTION: A clock generation circuit in a semiconductor integrated circuit outputs a clock signal to one or a plurality of internal circuits of the semiconductor integrated circuit, and includes a variable oscillation circuit and a selection circuit. The variable oscillation circuit generates a second clock signal, which is a clock signal based on one frequency, from a plurality of clock signals, and outputs the second clock signal. The selection circuit outputs any of the first clock signal input from the outside and the second clock signal input from the variable oscillation circuit. A clock signal output to the circuit is a clock signal generated on the basis of the clock signal output from the selection circuit.SELECTED DRAWING: Figure 1
Inventors:
Shimamura Kotaro
Naohiro Ikeda
Naohiro Ikeda
Application Number:
JP2018204235A
Publication Date:
November 16, 2022
Filing Date:
October 30, 2018
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F1/06; H03L7/08
Domestic Patent References:
| JP6177754A | ||||
| JP6140930A | ||||
| JP2011071816A | ||||
| JP5158572A | ||||
| JP2008234046A | ||||
| JP5077067B2 | ||||
| JP11143574A | ||||
| JP59195726A |
Foreign References:
| WO2008126239A1 |
Attorney, Agent or Firm:
Patent Business Corporation Sunnext International Patent Office